Image
Robots workplace etiquette
CSAIL article

Researchers at MIT’s Computer Science and Artificial Intelligence Laboratory (CSAIL) have developed a new framework called CommPlan that, rather than telling robots exactly when and how to communicate, gives them a few high-level principles for good etiquette and then leaves it to the robot to make decisions that would allow it to finish the task as efficiently as possible.

Image
robots do chores
MIT news article

Training interactive robots may one day be an easy job for everyone, even those without programming expertise. Roboticists are developing automated robots that can learn new tasks solely by observing humans. At home, you might someday show a domestic robot how to do routine chores. In the workplace, you could train robots like new employees, showing them how to perform many duties.

Image
TextFooler
MIT news article

A team from MIT’s Computer Science and Artificial Intelligence Laboratory (CSAIL) tested the boundaries of text. They came up with “TextFooler,” a general framework that can successfully attack natural language processing (NLP) systems — the types of systems that let us interact with our Siri and Alexa voice assistants — and “fool” them into making the wrong predictions. 

Image
road tagger
MIT news article

“Most updated digital maps are from places that big companies care the most about. If you’re in places they don’t care about much, you’re at a disadvantage with respect to the quality of map,” says co-author Sam Madden, a professor in the Department of Electrical Engineering and Computer Science (EECS) and a researcher in the Computer Science and Artificial Intelligence Laboratory (CSAIL). “Our goal is to automate the process of generating high-quality digital maps, so they can be available in any country.”

Image
faster computer chips
CSAIL article

“Modern computer processors are opaque, horrendously complicated, and difficult to understand. It is also incredibly challenging to write computer code that executes as fast as possible for these processors,” says co-author Michael Carbin, an assistant professor in the Department of Electrical Engineering and Computer Science (EECS). “This tool is a big step forward toward fully modeling the performance of these chips for improved efficiency.”