Joel Emer received his bachelor’s degree with the highest honors in electrical engineering in 1974, and his master’s degree in 1975 – both from Purdue University. And earned a doctorate in electrical engineering from the University of Illinois in 1979. Now, Emer is a professor of the Practice at MIT’s Electrical Engineering and Computer Science Department (EECS), a member of the Computer Science and Artificial Intelligence Laboratory (CSAIL), and a Senior Distinguished Research Scientist at Nvidia. Emer has held various research and advanced development position investigating processor micro-architecture and developing performance modeling and evaluation techniques. He has made architectural contributions to a number of VAX, Alpha and X86 processors and is recognized as one of the developers of the widely employed quantitative approach to processor performance evaluation.
Recent Works
Efficient Processing of Deep Neural Networks: A Tutorial and Survey
This research aims to provide a comprehensive tutorial and survey about the recent advances toward the goal of enabling efficient processing of DNNs. Specifically, it will provide an overview of DNN’s, discuss various hardware platforms and architectures that support DNNs, and highlight key trends in reducing the computation cost of DNNs either solely via hardware design changes or via joint hardware design and DNN algorithm changes.
Scavenger: Automating the Construction of Application-Optimized Memory Hierarchies
This research introduces Scavenger which utilizes spare resources to construct program-optimized memories and perform an initial exploration of methods for automating the construction of these applications-specific memory hierarchies. Although exploiting spare resources can be beneficial, naïvely consuming all memory resources may cause frequency degradation. To relieve timing pressure in large block RAM (BRAM) structures, this study provides microarchitectural techniques to trade memory latency for design frequency.
Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks
Eyeriss is an accelerator for state-of-the-art deep convolutional neural networks (CNNs). It optimizes for the energy efficiency of the entire system, including the accelerator chip and off-chip DRAM, for various CNN shapes by reconfiguring the architecture. CNNs are widely used in modern AI systems but also bring challenges on throughput and energy efficiency to the underlying hardware. Hence, Eyeriss uses a processing dataflow, called row stationary (RS), on a spatial architecture with 168 processing elements. RS dataflow reconfigures the computation mapping of a given shape, which optimizes energy efficiency by maximally reusing data locally to reduce expensive data movement, such as DRAM accesses.